`ifndef VERILATOR
module testbench;
  reg [4095:0] vcdfile;
  reg clock;
`else
module testbench(input clock, output reg genclock);
  initial genclock = 1;
`endif
  reg genclock = 1;
  reg [31:0] cycle = 0;
  reg [0:0] PI_write;
  reg [15:0] PI_Data_in;
  reg [0:0] PI_ip_resetn;
  reg [0:0] PI_global_resetn;
  reg [0:0] PI_Clk;
  register_write_once_example UUT (
    .write(PI_write),
    .Data_in(PI_Data_in),
    .ip_resetn(PI_ip_resetn),
    .global_resetn(PI_global_resetn),
    .Clk(PI_Clk)
  );
`ifndef VERILATOR
  initial begin
    if ($value$plusargs("vcd=%s", vcdfile)) begin
      $dumpfile(vcdfile);
      $dumpvars(0, testbench);
    end
    #5 clock = 0;
    while (genclock) begin
      #5 clock = 0;
      #5 clock = 1;
    end
  end
`endif
  initial begin
`ifndef VERILATOR
    #1;
`endif
    // UUT.$auto$async2sync.\cc:101:execute$67  = 1'b0;
    // UUT.$auto$async2sync.\cc:110:execute$71  = 1'b1;
    UUT._witness_.anyinit_procdff_45 = 1'b0;
    UUT._witness_.anyinit_procdff_46 = 1'b0;
    UUT._witness_.anyinit_procdff_47 = 1'b0;
    UUT._witness_.anyinit_procdff_48 = 1'b0;
    UUT._witness_.anyinit_procdff_49 = 1'b0;
    UUT._witness_.anyinit_procdff_50 = 1'b0;
    UUT._witness_.anyinit_procdff_51 = 1'b0;
    UUT._witness_.anyinit_procdff_52 = 15'b000000000000000;
    UUT._witness_.anyinit_procdff_57 = 16'b0000000000000000;
    UUT._witness_.anyinit_procdff_62 = 1'b0;

    // state 0
    PI_write = 1'b0;
    PI_Data_in = 16'b0000000000000000;
    PI_ip_resetn = 1'b0;
    PI_global_resetn = 1'b0;
    PI_Clk = 1'b0;
  end
  always @(posedge clock) begin
    // state 1
    if (cycle == 0) begin
      PI_write <= 1'b1;
      PI_Data_in <= 16'b1111111111111100;
      PI_ip_resetn <= 1'b1;
      PI_global_resetn <= 1'b0;
      PI_Clk <= 1'b0;
    end

    // state 2
    if (cycle == 1) begin
      PI_write <= 1'b1;
      PI_Data_in <= 16'b1111111111111111;
      PI_ip_resetn <= 1'b1;
      PI_global_resetn <= 1'b0;
      PI_Clk <= 1'b0;
    end

    // state 3
    if (cycle == 2) begin
      PI_write <= 1'b0;
      PI_Data_in <= 16'b0000000000000000;
      PI_ip_resetn <= 1'b1;
      PI_global_resetn <= 1'b0;
      PI_Clk <= 1'b0;
    end

    // state 4
    if (cycle == 3) begin
      PI_write <= 1'b0;
      PI_Data_in <= 16'b0000000000000000;
      PI_ip_resetn <= 1'b0;
      PI_global_resetn <= 1'b0;
      PI_Clk <= 1'b0;
    end

    genclock <= cycle < 4;
    cycle <= cycle + 1;
  end
endmodule
